Title :
Analyze the ATMOS configuration with VTH abolition logic in 4×1 MUX
Author :
Jain, Paril ; Akashe, Shyam
Author_Institution :
ITM Univ., Gwalior, India
Abstract :
A speculative configuration of MOS transistors with a threshold rejection technique is modified. The design configuration is analyzed logic in aspect cum internal threshold abolition (ITA) and discloses circuit imminent and recital confines. Consequent circuit equations exemplify the exchange between the voltage drop and the reverse leakage. Moreover, a circuit development process for the improvement of the power transmission efficiency (PTE) of a 4×1 MUX with ITA MOS configuration was modified based on the design. A 4×1 MUX was optimized and employed in a digital system 45-nm CMOS technology, and Cadence simulation experimental implementation results of the leakage power and PCE illustrate superior conformity through the proposed configuration.
Keywords :
CMOS logic circuits; MOSFET; integrated circuit design; leakage currents; multiplexing equipment; ´TA MOS configuration; 4x1 MUX; ATMOS configuration; CMOS; Cadence simulation; MOS transistors; PCE; V TH abolition logic; design configuration; internal threshold abolition; leakage power; power transmission efficiency; reverse leakage; size 45 nm; threshold rejection technique; voltage drop; CMOS integrated circuits; MOS devices; Manganese; Random access memory; Rectifiers; Switches; System-on-chip; Analog integrated circuits; power transmission efficiency; threshold abolition‥;
Conference_Titel :
Control Computing Communication & Materials (ICCCCM), 2013 International Conference on
Conference_Location :
Allahabad
Print_ISBN :
978-1-4799-1374-9
DOI :
10.1109/ICCCCM.2013.6648916
