Investigating diachrony of programmable microelectronic nanostructures

New technologies of design and manufacturing of advanced integrated circuits allow higher integration of complex structures in ultra-high nano-scale densities. The rapidly growing world of FPGA devices creates important platform for analyses of process scaling and new study opportunities in case of new process variations and degradation effects. However the real devices are not the ideal ones and they are subjects of aging of the internal nanostructures. Changes in parameters of FPGAs in time, or under either power supply voltage or temperature variations, can result in significant delays and may affect the final design quality and dependability. Such timing variations may result in delay faults, up to the final device or equipment malfunction or failure. Especially the world of ASIC devices is comprehensively investigated again and again with the new processes coming every (approximately) 2 years. This paper presents an unusual solution of the aging measurement, analysis and test unit, based on especially designed ring oscillators and utilization of the internal block RAMs (BRAM) in Xilinx FPGAs, selected from 65 nm down to the 40 nm technology node.