Analytical Modeling of the Suspended-Gate FET and Design Insights for Digital Logic

We present a new, analytical model for the SGFET that is suitable for hand calculations and time-efficient circuit simulations. Our model expresses the pull-in, pull-out voltages and the stable travel range in terms of the structural parameters and the moving gate position as a function of the gate voltage. Starting from our model, we discuss the influence of the structural parameters on the transistor characteristics and the potential of the SGFET for logic circuits. We also introduce the SGFET SRAM cell to demonstrate the use of our model and to illustrate the interest of the SGFET for ultra-low power applications. SGFET logic gates exhibit a significantly reduced off-state power dissipation and improved functionality as compared to CMOS gates.