• DocumentCode
    1958689
  • Title

    Architectures for arithmetic over GF(2m)

  • Author

    Barua, Rana ; Sengupta, Samik

  • Author_Institution
    Div. of Stat. Math., Indian Stat. Inst., India
  • fYear
    1997
  • fDate
    4-7 Jan 1997
  • Firstpage
    465
  • Lastpage
    468
  • Abstract
    Arithmetic over finite fields has significant applications in switching theory, error-correcting codes, cryptography etc. In this article, we present several algorithms and design architectures for some of the operations over GF(2m). The architectures use one-dimensional arrays with regular and nearest-neighbour interconnections. Together with a modification of a standard basis multiplier, our designs cover array-based implementations for all these operations for both normal and standard basis. We also design a normal basis multiplier which, for many values of m, has less complicated interconnections and by achieving squaring in standard basis in one clock cycle, we establish this basis as a practicable alternative to normal basis for fast and efficient arithmetic operations over GF(2m)
  • Keywords
    Galois fields; VLSI; digital arithmetic; logic arrays; GF(2m); arithmetic over finite fields; array-based implementations; cryptography; design architectures; error-correcting codes; nearest-neighbour interconnections; normal basis multiplier; one-dimensional arrays; squaring; standard basis; switching theory; Algorithm design and analysis; Arithmetic; Books; Clocks; Cryptography; Error correction codes; Galois fields; Integrated circuit interconnections; Polynomials; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design, 1997. Proceedings., Tenth International Conference on
  • Conference_Location
    Hyderabad
  • ISSN
    1063-9667
  • Print_ISBN
    0-8186-7755-4
  • Type

    conf

  • DOI
    10.1109/ICVD.1997.568178
  • Filename
    568178