DocumentCode :
1958750
Title :
Generating Toffoli networks from ESOP expressions
Author :
Sanaee, Yasaman ; Dueck, Gerhard W.
Author_Institution :
Fac. of Comput. Sci., Univ. of New Brunswick, Fredericton, NB, Canada
fYear :
2009
fDate :
23-26 Aug. 2009
Firstpage :
715
Lastpage :
719
Abstract :
In this paper a new heuristic ESOP-based synthesis method for Toffoli networks is proposed. This synthesis method takes advantage of the shared-ESOP cubes among the outputs to generate a cascade of Toffoli gates. The method is suitable to generate circuits for functions with large number of input variables. A greedy approach is utilized to select pairs among the different outputs with common ESOP-cubes. The shared terms need only to be realized once and the result can then be transferred to the second output, and thus reducing the number of Toffoli gates. The synthesis algorithm has been applied to a set of benchmark functions. Experimental results show that the algorithm can generate circuits with reduced quantum cost for virtually all functions. Template applications can further improve the results.
Keywords :
integrated circuit design; logic design; quantum gates; ESOP expression; ESOP-based synthesis; Toffoli gates; Toffoli network; greedy approach; quantum cost; shared-ESOP cubes; Boolean functions; Circuit synthesis; Computer science; Cost function; Data structures; Heuristic algorithms; Logic; Network synthesis; Optical computing; Quantum computing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Communications, Computers and Signal Processing, 2009. PacRim 2009. IEEE Pacific Rim Conference on
Conference_Location :
Victoria, BC
Print_ISBN :
978-1-4244-4560-8
Electronic_ISBN :
978-1-4244-4561-5
Type :
conf
DOI :
10.1109/PACRIM.2009.5291282
Filename :
5291282
Link To Document :
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