DocumentCode :
1958941
Title :
On identifying don´t care inputs of test patterns for combinational circuits
Author :
Kajihara, S. ; Miyase, K.
Author_Institution :
Dept. of Comput. Sci. & Electron., Kyushu Inst. of Technol., Iizuka, Japan
fYear :
2001
fDate :
4-8 Nov. 2001
Firstpage :
364
Lastpage :
369
Abstract :
Given a test set for stuck at faults, some of primary input values may be changed to opposite logic values without losing fault coverage. We can regard such input values as don´t care (X). In this paper, we propose a method for identifying X inputs of test vectors in a given test set. While there are many combinations of X inputs in the test set generally, the proposed method finds one including X inputs as many as possible, by using fault simulation and procedures similar to implication and justification of ATPG algorithms. Experimental results for ISCAS benchmark circuits show that approximately 66% of inputs of un-compacted test sets could be X in average. Even for compacted test sets, the method found that approximately 47% of inputs are X. Finally, we discuss how logic values are reassigned to the identified X inputs where several applications exist to make test vectors more desirable.
Keywords :
automatic test pattern generation; combinational circuits; fault simulation; logic testing; ATPG algorithm; combinational circuit; don´t care inputs; fault coverage; fault simulation; logic values; stuck-at fault; test pattern; Benchmark testing; Circuit faults; Circuit simulation; Circuit testing; Combinational circuits; Electronic equipment testing; Fault detection; Logic testing; Microelectronics; Test pattern generators;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Aided Design, 2001. ICCAD 2001. IEEE/ACM International Conference on
Conference_Location :
San Jose, CA, USA
ISSN :
1092-3152
Print_ISBN :
0-7803-7247-6
Type :
conf
DOI :
10.1109/ICCAD.2001.968648
Filename :
968648
Link To Document :
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