Title :
Multilevel approach to full-chip gridless routing
Author :
Cong, J. ; Fang, J. ; Zhang, Y.
Author_Institution :
Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
Abstract :
Presents a novel gridless detailed routing approach based on multilevel optimization. The multilevel framework with recursive coarsening and refinement in a "V-shaped" flow allows efficient scaling of the gridless detailed router to very large designs. The downward pass of recursive coarsening builds the representations of routing regions at different levels, while the upward pass of iterative refinement allows a gradual convergence to a globally optimized solution. The use of a multicommodity flow-based routing algorithm for the initial routing at the coarsest level and a modified maze algorithm for the refinement at each level considerably improves the quality of gridless routing results. Compared with the recently published gridless detailed routing algorithm using wire planning, the multilevel gridless routing algorithm is 3/spl times/ to 75/spl times/faster. We also compared the multilevel framework with a recently developed three-level routing approach and a traditional hierarchical routing approach.
Keywords :
VLSI; circuit layout CAD; circuit optimisation; iterative methods; network routing; wiring; V-shaped flow; completion rates; full-chip gridless routing; globally optimized solution; hierarchical routing approach; iterative refinement; maze algorithm; multicommodity flow-based routing algorithm; multilevel approach; multilevel optimization; recursive coarsening; routing regions; wire planning; Approximation algorithms; Computer science; Delay; Iterative algorithms; Partitioning algorithms; Routing; Silicon; Tiles; Very large scale integration; Wire;
Conference_Titel :
Computer Aided Design, 2001. ICCAD 2001. IEEE/ACM International Conference on
Conference_Location :
San Jose, CA, USA
Print_ISBN :
0-7803-7247-6
DOI :
10.1109/ICCAD.2001.968655