Title :
Faster fault simulation through distributed computing
Author :
Ravikumar, C.P. ; Jain, Vikas ; Dod, Anurag
Author_Institution :
Dept. of Electr. Eng., Indian Inst. of Technol., New Delhi, India
Abstract :
In this paper, we describe distributed algorithms for combinational fault simulation assuming the classical stuck-at fault model. Our algorithms have been implemented on a network of Sun workstations under the Parallel Virtual Machine (PVM) environment. Two techniques are used for subdividing work among processors -test set partition and fault set partition. The sequential algorithm for fault simulation, used on individual nodes of the network, is based on a novel path compression technique proposed in this paper. We describe experimental results on a number of ISCAS ´85 benchmark circuits
Keywords :
combinational circuits; distributed algorithms; fault diagnosis; logic partitioning; logic testing; parallel machines; virtual machines; ISCAS ´85 benchmark circuits; Sun workstation network; classical stuck-at fault model; combinational fault simulation; distributed algorithms; distributed computing; fault set partition; parallel virtual machine environment; path compression technique; sequential algorithm; test set partition; Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Computer simulation; Discrete event simulation; Distributed algorithms; Distributed computing; Partitioning algorithms; Very large scale integration;
Conference_Titel :
VLSI Design, 1997. Proceedings., Tenth International Conference on
Conference_Location :
Hyderabad
Print_ISBN :
0-8186-7755-4
DOI :
10.1109/ICVD.1997.568181
