Faster fault simulation through distributed computing

Author

Ravikumar, C.P. ; Jain, Vikas ; Dod, Anurag

Author_Institution

Dept. of Electr. Eng., Indian Inst. of Technol., New Delhi, India

fYear

1997

fDate

4-7 Jan 1997

Firstpage

482

Lastpage

487

Abstract

In this paper, we describe distributed algorithms for combinational fault simulation assuming the classical stuck-at fault model. Our algorithms have been implemented on a network of Sun workstations under the Parallel Virtual Machine (PVM) environment. Two techniques are used for subdividing work among processors -test set partition and fault set partition. The sequential algorithm for fault simulation, used on individual nodes of the network, is based on a novel path compression technique proposed in this paper. We describe experimental results on a number of ISCAS ´85 benchmark circuits

Keywords

combinational circuits; distributed algorithms; fault diagnosis; logic partitioning; logic testing; parallel machines; virtual machines; ISCAS ´85 benchmark circuits; Sun workstation network; classical stuck-at fault model; combinational fault simulation; distributed algorithms; distributed computing; fault set partition; parallel virtual machine environment; path compression technique; sequential algorithm; test set partition; Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Computer simulation; Discrete event simulation; Distributed algorithms; Distributed computing; Partitioning algorithms; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, 1997. Proceedings., Tenth International Conference on

Conference_Location

Hyderabad

ISSN

1063-9667

Print_ISBN

0-8186-7755-4

Type

conf

DOI

10.1109/ICVD.1997.568181

Filename

568181