A Low Power, Highly Scalable, Vertical Double Gate MOSFET Using Novel Processes

A sub-45nm body thickness, vertical channel, double gate MOSFETs (VDGFET) is fabricated on bulk-silicon substrate. The process, in principle, is scalable down to sub-5nm body thicknesses. It is realized using very coarse lithography (~1um resolution), does not require CMP, and is capable of being integrated with a planar CMOS flow. It relies on the following key, novel, unit processes: 1) A spacer process obtained using a new set of spacer materials, with demonstrated mask thickness down to 5nm, 2) a self-aligned process for achieving a thicker bottom/corner field isolation oxide, thus, minimizing leakage and parasitic capacitances, 3) a novel drain contact process including etch stop and implant, which overcomes the problem of contacting very thin pillars. Electrical results show excellent short channel effect (SCE) immunity including very low DIBL and GIDL effects. In addition, a close to ideal measured subthreshold slope (64mV/decade) results in a very high I_ON to I_OFF ratio.