InGaAs CMOS: a "Beyond-the-Roadmap" Logic Technology?

This talk will discuss the general issues associated with III-V CMOS that are enunciated above. It will also describe the authors´ research activities in the area of InGaAs HEMTs for logic. In particular, we will summarize the findings of a recent scaling study of InGaAs HEMTs down to 60 nm in gate length [1]. In this work, we fabricated HEMTs with a 70% InAs composition in the channel and with varying gate lengths and InAIAs barrier thicknesses (from 11 to 3 nm). This study resulted in devices that have substantially more current drive than state-of-the-art 65 nm CMOS at a voltage of 0.5 V. It also showed that InGaAs HEMTs scale according to a simple electrostatics law similar to fully-depleted SOI MOSFETs. Our research reveals that HEMTs are excellent test vehicles to study topics of great relevance to future III-V MISFETs, such as self-aligned device architectures, scaling limit of planar devices, impact of strain on transport physics, and the consequences of a low density of states on current drive of deeply scaled devices..