Title :
A high-level synthesizer for VLSI array architectures dedicated to digital signal processing
Author :
Huang, Tung-Hao ; Liu, Chi-Min ; Jen, Chein-Wei
Author_Institution :
Nat. Chiao Tung Univ., Hsinchu, Taiwan
Abstract :
A package, named VLSI array architectures synthesizer (VAAS), to synthesize VLSI array architectures for DSP applications is presented. VAAS has been imbedded with the systematical synthesis method for systolic arrays, two-level pipelined systolic arrays, and multiple-array architectures. It provides a design environment with an algorithm description language, 3D graphical representations, performance evaluation, array simulation, a library of systolic algorithms, etc. Based on the environment, feasible VLSI array architectures for a DSP application can be exploited quickly. Two design examples are used to demonstrate the package
Keywords :
VLSI; circuit CAD; computerised signal processing; systolic arrays; 3D graphical representations; VAAS; VLSI array architectures synthesizer; algorithm description language; array simulation; design environment; digital signal processing; multiple-array architectures; performance evaluation; systematical synthesis method; systolic algorithms; two-level pipelined systolic arrays; Algorithm design and analysis; Computer architecture; Design methodology; Digital signal processing; Packaging; Parallel processing; Signal processing algorithms; Synthesizers; Systolic arrays; Very large scale integration;
Conference_Titel :
Acoustics, Speech, and Signal Processing, 1991. ICASSP-91., 1991 International Conference on
Conference_Location :
Toronto, Ont.
Print_ISBN :
0-7803-0003-3
DOI :
10.1109/ICASSP.1991.150612