A Research on an ASIP Processing Element Architecture Suitable for FPGA Implementation

Application Specific Instruction Set Processors (ASIPs) combine the high processing speed of ASICs and the program abilities of DSPs, therefore can realize high parallelism and high processing speed with their parallel process-unit array architecture. The key problems in ASIP system designing are: the design of the programmable processing element (PE) and inter-PE communication mechanisms. A design of ASIP processing element which is suitable for FPGA implementation with RISC like architecture is introduced in the paper. The primary goal of this design is for digital image processing, but it is also suitable for the applications such as radar and communication signal processing. The carefully designed circuit structure and specific instruction set of proposed processing element make it universal, and thus can be tailored easily for many particular applications. The design of the ASIPpsilas functional units and the circuit utilization within the FPGA are presented with great detail and the correctness of the design is verified by some application results.