DocumentCode :
1960039
Title :
False-noise analysis using logic implications
Author :
Glebov, A. ; Gavrilov, S. ; Blaauw, D. ; Sirichotiyakul, S. ; Chanhee Oh ; Zolotov, V.
Author_Institution :
MicroStyle, Moscow, Russia
fYear :
2001
fDate :
4-8 Nov. 2001
Firstpage :
515
Lastpage :
521
Abstract :
Cross-coupled noise analysis has become a critical concern in VLSI design. Typically, noise analysis makes the assumption that all aggressing nets can simultaneously switch in the same direction. This creates a worst-case noise pulse on the victim net that often leads to false noise violations. In this paper, we present a new approach that uses logic implications to identify the maximum set of aggressor nets that can inject noise simultaneously under the logic constraints of the circuit. We propose an approach to efficiently generate logic implications from a transistor-level description and propagate them in the circuit using ROBDD representations of the DC-connected components and a newly proposed lateral propagation method. We then show that the problem of finding the worst case logically feasible noise can be represented as a maximum weighted independent set problem and show how to efficiently solve it. Initially, we restrict our discussion to zero-delay implications, which are valid for glitch-free circuits and then extend our approach to timed implications. The proposed approaches were implemented in an industrial noise analysis tool and results are shown for a number of industrial test cases. We demonstrate that a significant reduction in the number of noise failures can be obtained from considering the logic implications as proposed in this paper, underscoring the need for false-noise analysis.
Keywords :
VLSI; circuit CAD; circuit analysis computing; delays; integrated circuit design; integrated circuit interconnections; integrated circuit noise; logic CAD; logic simulation; timing; ROBDD representations; VLSI designs; VLSI interconnects; cross-coupled noise analysis; false noise violations; false-noise analysis; glitch-free circuits; industrial noise analysis tool; industrial test cases; lateral propagation method; logic constraints; logic implications; maximum aggressor net set; maximum weighted independent set problem; noise analysis; noise failures; simultaneous noise injection; simultaneously switching aggressing nets; timed implications; transistor-level description; victim net; worst case logically feasible noise; worst-case noise pulse; zero-delay implications; Capacitance; Circuit noise; Delay effects; Integrated circuit interconnections; Logic circuits; Noise reduction; Switches; Switching circuits; Timing; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Aided Design, 2001. ICCAD 2001. IEEE/ACM International Conference on
Conference_Location :
San Jose, CA, USA
ISSN :
1092-3152
Print_ISBN :
0-7803-7247-6
Type :
conf
DOI :
10.1109/ICCAD.2001.968695
Filename :
968695
Link To Document :
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