Title :
An improved space vector PWM method for a three-level inverter with reduced THD
Author :
Pratheesh, K.J. ; Jagadanand, G. ; Ramchand, Rijil
Author_Institution :
Electr. Eng. Dept., Nat. Inst. of Technol., Calicut, India
Abstract :
Among the multilevel inverters, the three-phase threelevel neutral point clamped (NPC) inverter is widely used for high power, medium voltage applications due to its superior performance compared to a two-level inverter. Proper control of such inverters is realized using modulation techniques, such as space vector pulse width modulation (SVPWM) which is having many advantages with reference to its implementation and harmonic reduction. This paper refers to a three phase three-level neutral point clamped inverter using space vector modulation technique. The algorithm to find the duty cycles of the inverter switches are based on the two-level inverter on-time calculations. An improved switching sequence is proposed in this paper to reduce the Total Harmonic Distortion (THD) in the line voltage and line current. The three-level inverter is simulated using the simplified algorithm and modified switching sequence. Harmonics analysis is carried out and compared with conventional SVPWM method.
Keywords :
PWM invertors; harmonic distortion; harmonics suppression; THD; harmonic analysis; harmonic reduction; inverter switches duty cycle; space vector PWM method; switching sequence; three-phase three-level neutral point clamped inverter; total harmonic distortion; Algorithm design and analysis; Clamps; Inverters; Mathematical model; Space vector pulse width modulation; Switches; Multilevel inverter; Neutral Point Clamped (NPC); Space Vector Pulse Width Modulation (SVPWM); Total Harmonic Distortion (THD); switching sequence; two-level inverter;
Conference_Titel :
Compatibility and Power Electronics (CPE), 2015 9th International Conference on
Conference_Location :
Costa da Caparica
DOI :
10.1109/CPE.2015.7231067