VLSI implementation of a 2-D DCT in a compiler

Author

Chau, Kwok K. ; Wang, I-Fay ; Eldridge, Creighton L.

Author_Institution

Texas Instrum., Dallas, TX, USA

fYear

1991

fDate

14-17 Apr 1991

Firstpage

1233

Abstract

A 100 MHz realization of a 2D DCT (discrete cosine transform) in a compiler is presented. An optimal nibble-serial distributed arithmetic architecture is used for an efficient direct implementation of the DCT. The compiler, which is based on BiCMOS gate array technology and functional module generation technology, is used to support a rapid prototyping environment. An 8×8 inverse 2D DCT example in a 0.8 μm BiCMOS gate array is given to illustrate the performance and flexibility of this approach. The design flow and a proposed development system, the Signal Analysis Workstation (SAW), are shown for customized system integrations

Keywords

BIMOS integrated circuits; VLSI; circuit layout CAD; digital signal processing chips; transforms; 0.8 micron; BiCMOS gate array; Signal Analysis Workstation; VLSI implementation; customized system integrations; design flow; development system; discrete cosine transform; function specific compiler; functional module generation; image processing; inverse 2D DCT; optimal nibble-serial distributed arithmetic architecture; rapid prototyping environment; Arithmetic; BiCMOS integrated circuits; Discrete cosine transforms; Instruments; Laboratories; Prototypes; Signal analysis; Signal design; Very large scale integration; Workstations;

fLanguage

English

Publisher

ieee

Conference_Titel

Acoustics, Speech, and Signal Processing, 1991. ICASSP-91., 1991 International Conference on

Conference_Location

Toronto, Ont.

ISSN

1520-6149

Print_ISBN

0-7803-0003-3

Type

conf

DOI

10.1109/ICASSP.1991.150616

Filename

150616