Challenges in power-ground integrity

With the advance of semiconductor manufacturing, EDA, and VLSI design technologies, circuits with increasingly higher speed are being integrated at an increasingly higher density. This trend causes correspondingly larger voltage fluctuations in the on-chip power distribution network due to IR-drop, L di/dt noise, or LC resonance. Therefore, power-ground integrity becomes a serious challenge in designing future high-performance circuits. In this paper, we introduce power-ground integrity, addressing its importance, verification methodology, and problem solution.