A folding transformation for VLSI IIR filter array design

An array structure of infinite impulse response (IIR) digital filters is presented. The architectures are formally derived using techniques for synthesizing systolic arrays from high-level (algorithmic) specifications. First, the authors apply the conventional synthesis techniques for deriving the array structure for IIR filters and then they discuss a folding transformation. Folding is a technique used for reducing the array size by allocating several computations onto the same processing element. It enables the designer to explore additional design options which are not available in the conventional approach of using linear projections to derive systolic arrays