FPGA based gate signal generator for three-level neutral point clamped inverters

The gate signals in a commercial three-phase two-level induction motor drive are translated to operate a three-phase three-level neutral point clamped (NPC) inverter. An FPGA is used to demodulate the two-level gate signals and then to generate NPC gate drive signals by re-modulation. A sine PWM modulation strategy with in-phase disposition of carriers is used to generate NPC gate drive signals. The modulation strategy is simulated first and then implemented using an Altera FPGA. The close match between the simulation and experimental results proves the concept and demonstrates the accuracy of this unique modulation technique.