Sustaining the Si revolution: challenges and opportunities

Continual advances in planar process technology enabled MOSFET gate lengths to reach below 100 nm in integrated circuits produced at the turn of the century, and will likely support MOSFET scaling into the sub-10 nm regime within the next 10 years. Gains in circuit performance will not be as straightforward to achieve as had been in the past, however, due to fundamental issues such as statistical dopant fluctuations, parasitic resistance and capacitance, and carrier velocity limits. This paper will first describe how these issues can be mitigated to allow transistor scaling to reach the quantum-mechanical limit. It will then discuss alternative approaches to achieving gains in system performance and cost as the era of transistor scaling draws to a close. Opportunities for research will be described.