CPNoC: On Using Constraint Programming in Design of Network-on-Chip Architecture

NoC technology is composed of switched-based interconnections, where the communication resources are shared. Therefore, the optimal resource utilization is a crucial consideration for the efficient architecture designs. Application mapping and scheduling are important optimization problems. This paper studies the practicality of the Constraint Programming (CP) models on NoC architecture designs that effectively use a regular mesh with wormhole switching and the XY routing. The complexity of the CP models is compared to the earlier Mixed Integer Programming (MIP) models. Practical CP-based mapping and scheduling models are developed and the results are reported on the benchmark datasets. The results indicate that mapping and scheduling problems can be solved at near optimality even under relatively shorter run-time limits compared to those required by the MIP models.