Design trade-offs in signal component separators for outphasing power amplifiers

Implementation design space of piece-wise linear outphasing signal component separator is explored by utilizing the changes in micro-architecture, choice of storage elements and aggressive back-end leakage power optimization techniques. With combination of these techniques, ~2× energy and area savings are achieved, resulting in record energy-efficiency of 32pJ/sample for asymmetric multilevel outphasing and 22pJ/sample for linear amplification with nonlinear components, at throughput of 400MSample/s and areas of 0.2-0.4mm² in 45nm SOI process.