A high speed compact priority encoder

A high-speed compact priority encoder for high-density parallel operations is developed. A simple and highly efficient CMOS technique is implemented for the construction of the priority resolution (PR) modules. The technique is based on a staircase array structure, and it is shown that the use of such an array reduces the hardware and causes parallel operations in the modules within the same level. This, in turn, reduces the overall time delay in the device by a large amount. A selective use of the precharge/predischarge scheme also provides a considerable reduction in the time response of the PR modules