Clock and data recovery circuits with fast acquisition and low jitter

This paper presents a half-rate clock and data recovery circuit (CDR) that combines the best features, fast acquisition and low jitter, of digital phase selection and phase-lock-loop (PLL) CDR circuits. This CDR circuit consists of a phase selector, which can lock to the data in just a few clock cycles but has high jitter, and a PLL, which requires a much longer lock time but provides a low-jitter clock after locking. Simulations in 1/2 micrometer CMOS technology show operation up to 800 Mbps, a 6% acquisition range, an initial acquisition time of 4 bit times with 211 ps rms jitter, and jitter of 7.5 ps after a PLL lock time of 650 ns. A phase-frequency magnitude detector (PFMD) is added to the combined CDR to improve the lock time by feeding back an estimate of the magnitude of the frequency offset in addition to the sign. Simulations show that the 650 ns lock time is reduced by about a factor of 4 to under 200 ns from an initial 6% frequency difference.