DocumentCode
1961865
Title
An integrated 80-V class-D power output stage with 94% efficiency in a 0.14µm SOI BCD process
Author
Haifeng Ma ; van der Zee, R. ; Nauta, Bram
Author_Institution
IC Design Group, Univ. of Twente, Enschede, Netherlands
fYear
2013
fDate
16-20 Sept. 2013
Firstpage
89
Lastpage
92
Abstract
In this paper we present a highly-efficient 80V class-D power stage design in a 0.14μm SOI-based BCD process. Immunity to the on-chip supply bounce is realized by internally regulated floating supplies, variable driving strength for the gate driver, and an efficient 2-step level shifter design. Fast switching transition and minimized switching loss are achieved with a 94% peak efficiency in the realized chip.
Keywords
CMOS integrated circuits; bipolar integrated circuits; power integrated circuits; silicon-on-insulator; 2-step level shifter design; SOI BCD process; Si; bipolar-CMOS-DMOS process; driving strength; fast switching transition; gate driver; integrated Class-D power output stage; internally regulated floating supplies; minimized switching loss; on-chip supply bounce; size 0.14 mum; voltage 80 V; Logic gates; Power transistors; Regulators; Switches; System-on-chip; Transistors; Voltage control;
fLanguage
English
Publisher
ieee
Conference_Titel
ESSCIRC (ESSCIRC), 2013 Proceedings of the
Conference_Location
Bucharest
ISSN
1930-8833
Print_ISBN
978-1-4799-0643-7
Type
conf
DOI
10.1109/ESSCIRC.2013.6649079
Filename
6649079
Link To Document