A low power zero-crossing pipeline-SAR ADC with on-chip dynamically loaded pre-charged reference

Author

Kuppambatti, Jayanth ; Kinget, Peter R.

Author_Institution

Columbia Univ., New York, NY, USA

fYear

2013

fDate

16-20 Sept. 2013

Firstpage

113

Lastpage

116

Abstract

A dynamically loaded pre-charged reference technique for low power zero-crossing pipeline-SAR ADCs is presented. Power hungry reference buffers are eliminated and the loading from the reference capacitors is also reduced, thus improving the ADC noise performance. The 65-nm CMOS ADC prototype has an SFDR/SNR/SNDR of 77dB/70dB/66dB at 25MHz, while consuming 4.8mW at 50MS/s, including all the power for the reference generation and distribution.

Keywords

CMOS integrated circuits; analogue-digital conversion; capacitors; integrated circuit noise; low-power electronics; prototypes; reference circuits; ADC noise performance; CMOS ADC prototype; frequency 24 MHz; low power zero-crossing pipeline-SAR ADC; on-chip dynamically loaded precharged reference; power 4.8 mW; reference capacitors; reference distribution; reference generation; size 65 nm; Capacitors; Linearity; Loading; Pipelines; Prototypes; Signal to noise ratio;

fLanguage

English

Publisher

ieee

Conference_Titel

ESSCIRC (ESSCIRC), 2013 Proceedings of the

Conference_Location

Bucharest

ISSN

1930-8833

Print_ISBN

978-1-4799-0643-7

Type

conf

DOI

10.1109/ESSCIRC.2013.6649085

Filename

6649085

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1962004