• DocumentCode
    1962018
  • Title

    An 8-bit 450-MS/s single-bit/cycle SAR ADC in 65-nm CMOS

  • Author

    Tripathi, Vaibhav ; Murmann, Boris

  • Author_Institution
    Dept. of Electr. Eng., Stanford Univ., Stanford, CA, USA
  • fYear
    2013
  • fDate
    16-20 Sept. 2013
  • Firstpage
    117
  • Lastpage
    120
  • Abstract
    A low-energy 8-bit 450-MS/s single-bit/cycle SAR ADC is presented. The design combines top-plate sampling, small unit capacitances (0.75 fF), symmetric DAC switching, and judicious delay optimization around a single high-speed comparator to achieve an ENOB of 7.6 at Nyquist, translating into an FOM of 76 fJ/conversion-step. The converter occupies an active area of 0.035 mm2 in 65-nm CMOS.
  • Keywords
    CMOS analogue integrated circuits; analogue-digital conversion; comparators (circuits); CMOS; ENOB; FOM; SAR ADC; capacitance 0.75 fF; delay optimization; single high-speed comparator; size 65 nm; symmetric DAC switching; top-plate sampling; word length 8 bit; CMOS integrated circuits; Capacitance; Clocks; Delays; Latches; Optimization; Switches;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    ESSCIRC (ESSCIRC), 2013 Proceedings of the
  • Conference_Location
    Bucharest
  • ISSN
    1930-8833
  • Print_ISBN
    978-1-4799-0643-7
  • Type

    conf

  • DOI
    10.1109/ESSCIRC.2013.6649086
  • Filename
    6649086
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1962018