Mapping applications on two-level configurable hardware

Implementing applications on Reconfigurable Computing Architectures (RCAs) is an important research topic because of their high potential to accelerate a wide range of functions. Nevertheless, configuring and programming RCAs is a long-standing challenge. In this paper, we propose a design methodology to map an algorithm on an FPGA preconfigured with a Coarse-Grained Reconfigurable Architecture (CGRA). At the lowest configuration level, the architecture of the CGRA is elaborated, synthesized, placed and routed by some hardware design specialist using suitable tools. At the highest level, someone who has no particular knowledge in hardware design is however able to configure the CGRA in order to map his algorithm on a mesh of parallel computing and communicating nodes. Nevertheless, for medium and large applications, where the number of nodes varies from tens to thousands, getting good mapping of applications becomes manually intractable. Founded on well known mapping and routing algorithms that we have tailored to match our context, we propose a design methodology to automate the mapping of applications on a two-level configurable adaptive hardware fabric. Preliminary experiments on Fast Fourier Transform (FFT) and matrix multiplication applications show that the proposed methodology can lead to high throughput and/or low latency within a reasonable design time.