Optimization of contact interface resistance for CMOS circuits

In this paper, we demonstrate optimizations within the sintering process window to reduce contact resistance and improve reliability after thermal cycling. A two-phase experiment is outlined to investigate these effects for blanket and localized ion implantation. In addition, a comparison of different aluminum-silicon alloys is performed across the process window of sintering conditions. SEM images are used to verify adequate filling of contact holes and EDS compositional analysis results are presented. I-V characteristics are then used to evaluate electrical performance of the ohmic contact. Recommendations for further improvement of contact formation for back end processes are made. Educational benefits to undergraduates are emphasized.