• DocumentCode
    1962208
  • Title

    A Transaction Level Assertion Verification Framework in SystemC: An Application Study

  • Author

    Tomasena, K. ; Sevillano, J.F. ; Pérez, J. ; Cortés, A. ; Vélez, I.

  • Author_Institution
    CEIT & TECNUN, Univ. of Navarra, San Sebastian, Spain
  • fYear
    2009
  • fDate
    11-16 Oct. 2009
  • Firstpage
    75
  • Lastpage
    80
  • Abstract
    This paper presents a new transaction level assertion verification framework built on top of SystemC to support the integration of assertion based verification in a model driven design methodology. A key point of the proposed framework is that it enables decoupling the work of the design and verification teams. This is possible thanks to data introspection capabilities; the fact that the assertions are not embedded in the design model code; and the abstraction in the property specification. Thus, the two teams can work in parallel starting from the natural language specification, reducing the development time.
  • Keywords
    program verification; SystemC; model driven design methodology; natural language specification; property specification; transaction level assertion verification framework; ANSI standards; Circuits; Computer architecture; Design methodology; Hardware; Libraries; Modeling; Natural languages; Programming; Workstations; Assertion Based Verification; SystemC; Transaction Level Modeling;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Advances in Circuits, Electronics and Micro-electronics, 2009. CENICS '09. Second International Conference on
  • Conference_Location
    Sliema
  • Print_ISBN
    978-0-7695-3832-7
  • Type

    conf

  • DOI
    10.1109/CENICS.2009.24
  • Filename
    5291497