Title :
Mitigation of variations in environmental conditions by SoPC architecture adaptation
Author :
Dumitriu, Victor ; Kirischian, Lev ; Kirischian, Valeri
Author_Institution :
Dept. of Electr. & Comput. Eng., Ryerson Univ., Toronto, ON, Canada
Abstract :
Run-time reconfigurable computing systems can offer increased flexibility when compared with traditional systems, a feature which can make them attractive for space-borne computing applications. This flexibility can allow a system to adapt to changes in operating conditions, such as reductions in available power, reductions in available resources (wither due to increases in task deployment, or due to permanent faults) or changes in required performance (processing rate). A unified mechanism which allows such adaptations is presented in this paper, based on the concept of architectural variants for a given algorithm; the different architectures exhibit different resource utilization, performance and power consumption attributes. This allows the system to meet various constraints through the judicious selection and deployment of an architecture variant by the appropriate reconfiguration of an implemented System-on Programmable Chip (SoPC). The adaptive capabilities of the proposed mechanism are experimentally tested on the Xilinx Kintex-7 FPGA platform (KC-705) using a video processing application aimed at 720p video streams. Three different versions of the application algorithm are implemented, allowing for performance variations between 3 and 300+ frames/second, while exhibiting a large power consumption range (from 1 mW to 81 mW).
Keywords :
field programmable gate arrays; power consumption; reconfigurable architectures; system-on-chip; video streaming; SoPC architecture adaptation; Xilinx Kintex-7 FPGA platform; appropriate reconfiguration; architectural variant; architecture variant; environmental condition; judicious selection; permanent fault; power consumption attribute; resource utilization; run-time reconfigurable computing system; space-borne computing application; system-on programmable chip; task deployment; video processing application; video stream; Adders; Circuit faults; Clocks; Computer architecture; Field programmable gate arrays; Power demand; Time-frequency analysis; FPGA; architecture design; dynamic partial reconfiguration; power consumption; run-time adaptation;
Conference_Titel :
Adaptive Hardware and Systems (AHS), 2015 NASA/ESA Conference on
Conference_Location :
Montreal, QC
DOI :
10.1109/AHS.2015.7231176