Microarchitectural optimization by means of reconfigurable and evolvable cache mappings

Physical limits are pushing chip manufacturer towards multi- and many-core architectures to maintain the progress of computing power. This trend has also emphasized reconfigurable computing, which enables for even higher parallelization degrees. Reconfigurable computing is often used together with a conventional processor to accelerate highly specific applications. However, exploiting dynamically reconfigurable systems for microarchitectural optimization is a novel research area. This paper presents for the first time an FPGA-based implementation of a processor that can reconfigure and adapt its own memory-to-cache address mapping function at runtime by means of dynamic reconfiguration and nature-inspired optimization. In experiments we can achieve up to 7.8% better execution times compared to a processor with a conventional cache mapping function.