A simulation methodology for assessing the impact of spatial/pattern dependent interconnect parameter variation on circuit performance

In this paper, we illustrate a methodology for determining the impact of interconnect pattern dependent variation on circuit performance. The methodology helps enable first pass prediction and can handle large layouts using methods which are reasonably compatible with existing CAD tools. We illustrate the relative utility of the methodology using two case studies. Both studies are drawn from industrial relevant problems: unwanted skew in a balanced clock tree and capacitance variation of a critical net in an SRAM array.