Optimizing dynamic-threshold DTMOS device performance in an SOI embedded DRAM technology

Author

Burke, F. ; Kim, C.S. ; Rambhatla, A. ; Zhao, Y. ; Zahurak, J. ; Parke, S.

Author_Institution

Dept. of Electr. & Comput. Eng., Boise State Univ., ID, USA

fYear

2003

fDate

30 June-2 July 2003

Firstpage

292

Lastpage

294

Abstract

This paper describes the DC and high frequency characteristics of a dynamic threshold DTMOS n-channel device, fabricated within a low-cost CMOS SOC process which also includes high-density embedded DRAM. The DTMOS device design in this process was previously found to be superior to both grounded body (GB) and floating body (FB) MOSFETs. This DTMOS device achieves kink-free behavior, with gm=936 μS/μm, g_out=36 μS/μm, Ion/Ioff=210 μA/0.1 pA, S=67 mV/dec, and fmax=32 GHz at V_DD=1 V. These DTMOS devices are excellent for sub-volt embedded baseband circuits with sufficient performance for RF front-end circuits, thus enabling the combination of embedded DRAM, digital, analog, and RF circuit cores in, ultra-low-power, low-cost SOCs.

Keywords

DRAM chips; MOSFET; silicon-on-insulator; system-on-chip; CMOS SOC process; DC characteristics; MOS device design; MOS n-channel device; MOSFET; RF front-end circuits; SOI embedded DRAM technology; Si; digital-analog combination circuit cores; dynamic-threshold MOS device; high frequency characteristics; silicon-on-insulator; subvolt embedded baseband circuits; system-on-chip; CMOS process; CMOS technology; Circuit testing; MOS devices; MOSFETs; Parasitic capacitance; Radio frequency; Random access memory; System testing; Transconductance;

fLanguage

English

Publisher

ieee

Conference_Titel

University/Government/Industry Microelectronics Symposium, 2003. Proceedings of the 15th Biennial

ISSN

0749-6877

Print_ISBN

0-7803-7972-1

Type

conf

DOI

10.1109/UGIM.2003.1225746

Filename

1225746