DocumentCode :
1962792
Title :
Parallel decoder for cellular automata based byte error correcting code
Author :
Chattopadhyay, S. ; Chaudhuri, P. Pal
Author_Institution :
Dept. of Comput. Sci. & Tech., Bengal Eng. Coll., Howrah, India
fYear :
1997
fDate :
4-7 Jan 1997
Firstpage :
527
Lastpage :
528
Abstract :
In this paper a new design scheme has been reported for parallel implementation of CA based SbEC/DbED and DbEC/DbED code that is analogous to the conventional Reed-Solomon code
Keywords :
Reed-Solomon codes; cellular automata; decoding; error correction codes; DbEC/DbED code; Reed-Solomon code; SbEC/DbED code; byte error correcting code; cellular automata; design; parallel decoder; Buildings; Concurrent computing; Decoding; Error correction codes; Hardware; High level synthesis; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design, 1997. Proceedings., Tenth International Conference on
Conference_Location :
Hyderabad
ISSN :
1063-9667
Print_ISBN :
0-8186-7755-4
Type :
conf
DOI :
10.1109/ICVD.1997.568197
Filename :
568197
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=1962792
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