A 0.4 GHz – 4 GHz direct RF-to-digital ΣΔ multi-mode receiver

A wide-tuning-range low-power sigma-delta-based direct-RF-to-digital receiver architecture is implemented in 65 nm CMOS. A multi-level (two-bit) non-return-to-zero DAC improves jitter immunity to enable a high dynamic range, and, with a class-AB low-noise transconductance amplifier guarantees a highly linear front end. The peak SNDR of the receiver exceeds 68 dB for a 4 MHz signal, and is better than 60 dB across the 400 MHz to 4 GHz carrier frequency range. By virtue of utilizing a negative feedback digitizer close to the antenna, an IIP3 of +10 dBm and an IIP2 of +50 dBm is achieved while dissipating only 40 mW from 1.1 V / 1.5 V supply voltages.