DocumentCode
1962949
Title
A low-voltage low-power 1.5 GHz CMOS LNA design
Author
Liu, Zhangfa ; Parke, Stephen
Author_Institution
Dept. of Electr. & Comput. Eng., Boise State Univ., ID, USA
fYear
2003
fDate
30 June-2 July 2003
Firstpage
340
Lastpage
341
Abstract
A low-voltage and low-power 1.5 GHz low-noise amplifier in 0.18 μm CMOS technology for GPS application is designed, this LNA has 28.7 dB gain with 0.2 dB noise figure from 1.0 V supply voltage. Basic noise analysis and design method are presented in this paper.
Keywords
CMOS integrated circuits; Global Positioning System; amplifiers; circuit noise; low-power electronics; receivers; 0.2 dB; 1.0 V; 1.5 GHz; 28.7 dB; CMOS LNA design; CMOS technology; GPS receiver; Global Positioning System; complementary metal-oxide-semiconductor; low-noise amplifier; low-voltage low-power amplifier; noise analysis; noise figure; CMOS technology; Circuit simulation; Energy consumption; Equations; Global Positioning System; Low-noise amplifiers; MOSFET circuits; Narrowband; Noise figure; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
University/Government/Industry Microelectronics Symposium, 2003. Proceedings of the 15th Biennial
ISSN
0749-6877
Print_ISBN
0-7803-7972-1
Type
conf
DOI
10.1109/UGIM.2003.1225760
Filename
1225760
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