DocumentCode
1962968
Title
Low-latency multiple clock domain interfacing without alteration of local clocks
Author
Smith, Scott F. ; Frenzel, James F.
Author_Institution
Boise State Univ., ID, USA
fYear
2003
fDate
30 June-2 July 2003
Firstpage
342
Lastpage
343
Abstract
A method for interfacing synchronous blocks of logic with different local clocks is presented which introduces very little latency and avoids metastability. The method does not require stopping or stretching local clocks and enforces correct operation of a bundled data constraint for all but very wide data paths.
Keywords
asynchronous circuits; clocks; integrated logic circuits; clock domain interfacing; interfacing synchronous blocks; latency multiple; metastability; stopping; stretching local clocks; Clocks; Conductors; Costs; Delay; Flip-flops; Inverters; Logic design; Metastasis; Pulse generation; Synchronization;
fLanguage
English
Publisher
ieee
Conference_Titel
University/Government/Industry Microelectronics Symposium, 2003. Proceedings of the 15th Biennial
ISSN
0749-6877
Print_ISBN
0-7803-7972-1
Type
conf
DOI
10.1109/UGIM.2003.1225761
Filename
1225761
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