High-resolution and wide-dynamic range time-to-digital converter with a multi-phase cyclic Vernier delay line

Author

Mino Kim ; Woo-Yeol Shin ; Gi-Moon Hong ; Jihwan Park ; Joo-Hyung Chae ; Nan Xing ; Jong-Kwan Woo ; Suhwan Kim

Author_Institution

Electr. Eng., Seoul Nat. Univ., Seoul, South Korea

fYear

2013

fDate

16-20 Sept. 2013

Firstpage

311

Lastpage

314

Abstract

In this paper, we propose a time-to-digital converter (TDC) that uses a multi-phase cyclic Vernier delay line (VDL) to achieve the high-resolution and wide-dynamic range. Its control voltages are provided by two phase-locked loops (PLLs) to compensate for the process and ambient variations. The two PLLs share a single reference clock and have different frequency-division ratios. It also improves the resolution of the TDC. A prototype chip, designed and fabricated in 0.18μm CMOS technology with an active area of 0.40mm², achieves a 3.4ps of resolution and an input range of 100ns at 2.5M samples/s, while consuming 32mW from a 1.8V supply.

Keywords

CMOS integrated circuits; delay lines; phase locked loops; time-digital conversion; CMOS technology; TDC; VDL; frequency-division ratio; multiphase cyclic Vernier delay line; phase locked loops; power 32 mW; reference clock; size 0.18 mum; time-to-digital converter; voltage 1.8 V; wide dynamic range; CMOS integrated circuits; Clocks; Delay lines; Delays; Dynamic range; Phase locked loops; Radiation detectors;

fLanguage

English

Publisher

ieee

Conference_Titel

ESSCIRC (ESSCIRC), 2013 Proceedings of the

Conference_Location

Bucharest

ISSN

1930-8833

Print_ISBN

978-1-4799-0643-7

Type

conf

DOI

10.1109/ESSCIRC.2013.6649135

Filename

6649135