Simulation of timing jitter in ring oscillators

Timing jitter is a concern in high-speed digital circuits, the presence of timing jitter will degrade system performance in many high speed applications. In this paper, we have simulated the timing jitter due to device noise in a nine stage CMOS differential ring oscillator and silicon BJT/or SiGe HBT ECL ring oscillator, and a methodology to efficiently simulate timing jitter has been developed. Simulation results are consistent with accepted theory and two important parameters cycle jitter and cycle to cycle jitter can be obtained from simulation. Simulation results are also compared with measurement and good agreement was observed between them. We also show BJT/or SiGe HBT oscillators have lower jitter compared to their CMOS counterparts. As such silicon BJT and/or SiGe HBT ring oscillators are a potential choice for low jitter applications. The methodology described in this paper is also applicable to other types of clock generator and oscillators such as LC oscillators, as well as other kinds of noise source as power supply and substrate noise.