A new hierarchical genetic algorithm for low-power network on chip design

A new hierarchical genetic algorithm for low-power network on chip (NoC) design is proposed in this paper. As 2D-mesh is a widely used NoC topology, this paper studies the optimization of mapping IP (intellectual property) cores onto regular and irregular 2D-mesh network while minimizing communication power consumption. Experimental results show that significant energy savings can be achieved. For instance, for a given application, up to 39% energy savings have been observed.