A 40MHz-BW two-step open-loop VCO-based ADC with 42fJ/step FoM in 40nm CMOS

Author

Xinpeng Xing ; Peng Gao ; Gielen, G.

Author_Institution

Dept. of Elektrotech., KU Leuven, Leuven, Belgium

fYear

2013

fDate

16-20 Sept. 2013

Firstpage

327

Lastpage

330

Abstract

A two-step open-loop VCO-based ADC with 1^st-order noise shaping and intrinsic nonlinearity mitigation is presented. With the open-loop structure and highly digital building blocks, a robust performance, high bandwidth and high efficiency is achieved. The nonlinearities of the VCOs in the coarse and fine quantizers are improved by a distortion cancellation and a voltage swing reduction scheme respectively. Because of the intrinsic DEM of the VCO-based quantizer output, the matching requirement of the DAC cells is greatly relaxed. The design is implemented in 40nm CMOS and shows that, with 1.6GHz sampling frequency, the two-step VCO-based ADC reaches 40MHz bandwidth, 59.5dB SNDR and 67.7dB SFDR. The power consumption is only 2.57mW, corresponding to an excellent FoM of 42fJ/step.

Keywords

CMOS integrated circuits; analogue-digital conversion; integrated circuit noise; low-power electronics; voltage-controlled oscillators; 1^st-order noise shaping; CMOS technology; bandwidth 40 MHz; distortion cancellation; frequency 1.6 GHz; intrinsic DEM; intrinsic dynamic element matching; intrinsic nonlinearity mitigation; power 2.57 mW; size 40 nm; two-step open-loop VCO-based ADC; voltage swing reduction scheme; Bandwidth; CMOS integrated circuits; Noise; Nonlinear distortion; Power demand; Quantization (signal); Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

ESSCIRC (ESSCIRC), 2013 Proceedings of the

Conference_Location

Bucharest

ISSN

1930-8833

Print_ISBN

978-1-4799-0643-7

Type

conf

DOI

10.1109/ESSCIRC.2013.6649139

Filename

6649139