DocumentCode :
1963117
Title :
A global code scheduling technique using guarded PDG
Author :
Koseki, Akira ; Komatsu, Hideaki ; Fukazawa, Yoshiaki
Author_Institution :
Sch. of Sci. & Eng., Waseda Univ., Tokyo, Japan
Volume :
2
fYear :
1995
fDate :
19-21 Apr 1995
Firstpage :
661
Abstract :
For instruction-level parallel machines, it is essential to extract parallelly executable instructions from a program by code scheduling. In this paper, we propose a new code scheduling technique using an extension of PDG. This technique parallelizes non-numerical programs, producing better machine codes than these created by percolation scheduling
Keywords :
parallel programming; scheduling; code scheduling; guarded PDG; high-performance computers; target architecture; Arithmetic; Computer aided instruction; Concurrent computing; Dynamic scheduling; Laboratories; Processor scheduling;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Algorithms and Architectures for Parallel Processing, 1995. ICAPP 95. IEEE First ICA/sup 3/PP., IEEE First International Conference on
Conference_Location :
Brisbane, Qld.
Print_ISBN :
0-7803-2018-2
Type :
conf
DOI :
10.1109/ICAPP.1995.472253
Filename :
472253
Link To Document :
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