A 105-dB SNDR, 10 kSps multi-level second-order incremental converter with smart-DEM consuming 280 µW and 3.3-V supply

This paper presents a second-order 3-bit incremental converter, which uses a novel Smart-DEM algorithm for mismatch compensation of multi-level DAC unity elements. The circuit, fabricated in a mixed 0.18-0.5-μm CMOS technology, achieves more than 17-bit resolution over a 5-kHz bandwidth using 256 clock periods. A single-step chopping of the input stage leads to a residual offset of 9.7 μV. The measured SFDR and power consumption are -90 dB and 280 μW, respectively. The achieved Figure of Merit is 177.5 dB.