On design of multiple-valued static random-access-memory

Author

Ishizuka, Okihiko ; Tang, Zheng ; Matsumoto, Hiroki

Author_Institution

Dept. of Electron. Eng., Miyazaki, Univ., Japan

fYear

1990

fDate

23-25 May 1990

Firstpage

11

Lastpage

17

Abstract

General theories on multiple-valued static random-access memory (RAM) are investigated. The criteria for a stable and an unstable mode are proved with strict mathematical methods and expressed with diagrammatic representation. A circuit design and realization for NMOS six-transistor ternary and quaternary static RAM cells based on the theories are proposed and simulated with PSPICE. A 10-valued CMOS current-mode static RAM cell is also presented and fabricated with standard 5-μm CMOS technology. Both PSPICE simulations and experiments indicate that the general theories presented are very useful and effective tools in optimal design and circuit realization of multiple-valued static RAMs

Keywords

logic design; many-valued logics; random-access storage; PSPICE simulations; circuit design; multiple-valued; static random-access memory; CMOS logic circuits; CMOS technology; Circuit simulation; Circuit synthesis; Equations; MOS devices; Random access memory; Read-write memory; SPICE; Sufficient conditions;

fLanguage

English

Publisher

ieee

Conference_Titel

Multiple-Valued Logic, 1990., Proceedings of the Twentieth International Symposium on

Conference_Location

Charlotte, NC

Print_ISBN

0-8186-2046-3

Type

conf

DOI

10.1109/ISMVL.1990.122585

Filename

122585