Title : 
An algorithm for finding a non-trivial lower bound for channel routing
         
        
            Author : 
Pal, Rajat K. ; Pal, Sudebkumar P. ; Pal, Ajit
         
        
            Author_Institution : 
Dept. of Comput. Sci., Calcutta Univ., India
         
        
        
        
        
        
            Abstract : 
Channel routing is a key problem in the physical design of VLSI chips. It is known that max(dmax,vmax) is a lower bound on the number of tracks required in the reserved two-layer Manhattan routing model, where dmax is the channel density and vmax is the length of the longest path in the vertical constraint graph. In this paper we propose a polynomial time algorithm that computes a better and non-trivial lower bound on the number of trades required for routing a channel without doglegging. This algorithm is also applicable for computing a lower bound on the number of tracks in the three-layer no-dogleg HVH routing as well as two- and three-layer restricted dogleg routing models
         
        
            Keywords : 
VLSI; graph theory; integrated circuit design; network routing; VLSI design; channel routing problem; nontrivial lower bound; polynomial time algorithm; three-layer no-dogleg HVH routing model; three-layer restricted dogleg routing model; two-layer Manhattan routing model; two-layer restricted dogleg routing model; vertical constraint graph; Algorithm design and analysis; Art; Councils; Polynomials; Routing; Very large scale integration; Wire;
         
        
        
        
            Conference_Titel : 
VLSI Design, 1997. Proceedings., Tenth International Conference on
         
        
            Conference_Location : 
Hyderabad
         
        
        
            Print_ISBN : 
0-8186-7755-4
         
        
        
            DOI : 
10.1109/ICVD.1997.568200