Title :
Dynamic fault grouping for PROOFS: a win for large sequential circuits
Author :
Graham, Charles R. ; Rudnick, Elizabeth M. ; Patel, Janak H.
Author_Institution :
Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
Abstract :
This paper discusses the important role of fault grouping in a parallel 32-bit fault simulator such as PROOFS. Three algorithms are presented which dynamically order the fault list during fault simulation to determine how the faults get grouped together. The dynamic fault grouping algorithms were incorporated into PROOFS and tested on benchmark circuits. The algorithms showed a marked reduction in the number of faulty circuit gate evaluations (compared to a static fault grouping) for almost all of the circuits with more than 20 flip-flops. For the largest benchmark circuit, s35932, all of the algorithms showed at least a 39% reduction in the number of faulty circuit gate evaluations and at least a 55% speedup in simulation time
Keywords :
circuit analysis computing; fault diagnosis; flip-flops; logic CAD; logic testing; sequential circuits; PROOFS; benchmark circuits; dynamic fault grouping; fault list ordering; fault simulator; faulty circuit gate evaluations; flip-flops; gate evaluations; large sequential circuits; simulation time; Benchmark testing; Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Concurrent computing; Flip-flops; Heuristic algorithms; Parallel processing; Sequential circuits;
Conference_Titel :
VLSI Design, 1997. Proceedings., Tenth International Conference on
Conference_Location :
Hyderabad
Print_ISBN :
0-8186-7755-4
DOI :
10.1109/ICVD.1997.568204
