DocumentCode :
1963508
Title :
Study of non-solder, low cost and high performance flip chip QFN package using ultra thin Pd PPF
Author :
Park, Se Chuel ; Cho, Chullae ; Paek, Sung-Kwan
Author_Institution :
Semicond. Mater. Div., Samsung Techwin Co., Ltd., Gyeongsangnam-Do, South Korea
fYear :
2003
fDate :
16-18 July 2003
Firstpage :
31
Lastpage :
37
Abstract :
For the development of semiconductor package, size reduction and high performance are driving forces. As increasing hand held products and green round issue, all package companies are interesting in study of package using lead free solder. As the today´s package trend, many kinds of flip chip packages are developed using lead free solder. In most of flip chip packages, lead free solder or Au has been employed mainly as wafer bump, and Sn or Ag plated leadframe based on copper as a substrate. Solder as an interconnection material has been adopted. This study describes the performance of low cost, non-solder and green round package using flip chip interconnection technology on a Pd pre-plated leadframe (Pd PPF). The conventional leadframe couldn´t be heated over 270 because of copper peel off. Although Pd-PPF could be workable in higher temperature than other type Cu leadframes, Conventional Pd-PPF showed that the poor thermal resistance for flip chip bonding process at high temperature. Therefore, in this study, newly developed a high quality and ultra thin Pd-PPF (AuAg finished Pd PPF) could provide proper surface condition and soluble substances. This leadframe could be applied to flip chip interconnection in wide temperature range. In conception of low cost, the electroless Ni/Au bump was used for flip chip interconnection with AuAg finished Pd PPF. The shear force of direct-bonded package was 23.05 mgf/μm2. We used thermal compression bonding method and bonding condition is as following: chip temperature 380 and leadframe 380. As leadframe temperature being increased, shear force of the package was very steeply increased. The interconnected layer between the bump and the pre-plated leadframe was composed of Ni/AuAg/Pd/Ni.
Keywords :
flip-chip devices; integrated circuit interconnections; integrated circuit packaging; lead bonding; solders; thermal resistance; 270 degC; 380 degC; Ag plated leadframe; Cu; Cu leadframes; Ni-AuAg-Pd-Ni; Pd; Sn plated leadframe; chip temperature; copper peel; electroless Ni/Au bump; flip chip QFN package; flip chip bonding process; flip chip interconnection technology; green round package; lead free solder; leadframe temperature; semiconductor package; shear force; thermal compression bonding method; thermal resistance; ultra thin Pd pre-plated leadframe; wafer bump; Bonding; Copper; Costs; Environmentally friendly manufacturing techniques; Flip chip; Gold; Lead; Semiconductor device packaging; Temperature; Thermal resistance;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics Manufacturing Technology Symposium, 2003. IEMT 2003. IEEE/CPMT/SEMI 28th International
ISSN :
1089-8190
Print_ISBN :
0-7803-7933-0
Type :
conf
DOI :
10.1109/IEMT.2003.1225874
Filename :
1225874
Link To Document :
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