Title :
A &thetas;(log n) algorithm for modulo multiplication
Author :
Elleithy, K.M. ; Bayoumi, M.A.
Author_Institution :
Univ. of Southwestern Louisiana, Lafayette, LA, USA
Abstract :
A θ(log n) algorithm for large moduli multiplication for residue-number-system (RNS)-based architectures is proposed. The modulo multiplier is much faster than previously proposed multipliers, and more area efficient. The implementation of the multiplier is modular and is based on simple cells, which leads to efficient VLSI realization. A VLSI implementation using 3-μm CMOS process shows that a pipelined n-bit modulo multiplication scheme can operate with a throughput of 30M operations/s
Keywords :
CMOS integrated circuits; VLSI; digital arithmetic; logic arrays; multiplying circuits; pipeline processing; &thetas;(log n) algorithm; 3 micron; CMOS process; RNS-based architecture; VLSI implementation; array adder; modulo multiplication; pipelined scheme; residue-number-system; Arithmetic; Kernel; Multiplexing; Table lookup;
Conference_Titel :
Circuits and Systems, 1989., Proceedings of the 32nd Midwest Symposium on
Conference_Location :
Champaign, IL
DOI :
10.1109/MWSCAS.1989.101864
