A design and performance study of 3D packaging for high performance memory applications

To address the performance and miniaturization challenges being faced by the packaging industry, a novel packaging methodology is presented in this paper. A 3D packaging methodology that leverages the existing CSP (Chip Scale Packaging) infrastructure to design and build memory solutions that is high performing and highly dense is presented. The design includes the individual device package design, the 3D package design and module design. Both the electrical and thermal performance is optimized by modifying the three levels of design. The design trade-offs are studied in terms of performance and compared to the performance of single device packages. The 3D packages are analyzed electrically and thermally using finite element and finite difference-based commercial software. The electrical performance results are presented at a single device level and at the 3D package level. The thermal performance is determined under standard test conditions and actual operating environments. Finally, to illustrate the 3D packaging technique, a compact memory module is presented that offers high performance, has a low profile and enables dense memory systems.