An IEEE Compliant Floating-Point Adder with the Deeply Pipelining Paradigm on FPGAs

FPGAs are increasingly being used to design high-end computationally intense microprocessors capable of implementing floating-point operations based hardware accelerators. In this paper, the throughput was improved by increasing the number of pipelining stages of the floating-point adder, and the feasibility of advancing the system clock rate was researched by making the most of plenty of flip-flops in FPGAs. The multi-paths floating-point adder/subtractor architecture that was the separate exponents/mantissas operations and the separate addition/subtraction datapaths was presented. On Alterapsilas Stratix II series FPGA, we achieved throughput rates more than 375 MHz (329 MHz) for single (double) precision operations by 8(12)-stages deeply pipelining units.